Disributed Memory and Control Vlsi Architectures for the 1-d Discrete Wavelet Transform 1

We address the synthesis of fast, eecient and regular computational structures for the Discrete Wavelet Transform (DWT) algorithm , using linear space-time mapping and constraint driven localization techniques. Index space transformations are used to regularize the DWT algorithm and to avoid data collisions due to multiprojection. A summary of the data dependence and localization analysis is presented, as well as an array of L Processing Elements (PEs) for computing any J-octave DWT decomposition with latency of M, where L is the wavelet lter length and M is the input sequence length. The latency is independent of the highest computable octave J, for any value of J, and the eeciency is nearly optimal and independent of M. The proposed design is the fastest parallel implementation of the 1-D DWT with L PEs that we know of.